By Bruno Zatt, Muhammad Shafique, Sergio Bampi, Jörg Henkel (auth.)
This e-book exhibits readers easy methods to boost energy-efficient algorithms and architectures to permit high-definition 3D video coding on resource-constrained embedded units. clients of the Multiview Video Coding (MVC) usual face the problem of exploiting its 3D video-specific coding instruments for expanding compression potency on the rate of accelerating computational complexity and, as a result, the power intake. This e-book permits readers to lessen the multiview video coding strength intake via together contemplating the algorithmic and architectural degrees. insurance comprises an creation to 3D movies and an in depth dialogue of the present state of the art of 3D video coding, in addition to energy-efficient algorithms for 3D video coding and energy-efficient structure for 3D video coding.
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Extra info for 3D Video Coding for Embedded Devices: Energy Efficient Algorithms and Architectures
For instance, most of the traditional ME fast search patterns perform badly for DE. The reason is that motion vectors are usually located in a relative small length range while disparity vectors usually are much longer. The disparity vectors frequently have 50–100 samples length. For this reason, the recommended search range is at least [±96,±96] for SD resolutions (Xu and He 2008). In this scenario most of the fast algorithms tend to fall in local minima and do not find the optimal candidate. For this reason the JMVC, the reference software for MVC (JVT 2009a, b), implements the TZ Search that is more complex in comparison to DS and EPZS, for example, but is still 23× times faster than FS (Yang 2009).
14, for instance an SR [±16,±16] covers an SW of 33 × 33 samples. Many search schemes for ME were proposed along the last two decades and their characteristics are well known. 3 Multiview Video Coding 25 effort. Many fast algorithms focusing on complexity reduction with small quality loss are found such as Log Search (JVT 2009a, b), Diamond Search (DS) (Kuhn 1999), Three Step Search (TSS) (Jing and Chau 2004a), UMHexagon Search (Chen et al. 2002) and Enhanced Predictive Zonal Search (EPZS) (Tourapis 2002), to list a few.
2010) an architectural template for run-time scalable systolic coprocessors is presented. It focuses on run-time adaptation to time-variable tasks or changing system conditions. It exploits replacing and relocation of basic processing elements of the array using FPGAs dynamic reconfiguration. In Beck et al. (2008) is employed a coarse-grained reconfigurable array with a run-time mechanism designed to translate MIPS instruction to be executed in the reconfigurable array. Berekovic et al. 264/AVC to the ADRES (coarse-grain reconfigurable processor) delivering throughput for real-time CIF decoding at 50 MHz with a 4 × 4-core array.
3D Video Coding for Embedded Devices: Energy Efficient Algorithms and Architectures by Bruno Zatt, Muhammad Shafique, Sergio Bampi, Jörg Henkel (auth.)